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Microchip Technology DSC6101JI3B-100.0000T — Crystals & Oscillators

Microchip DSC6101JI3B-100.0000T MEMS XO, 100 MHz, AEC-Q100

MPNDSC6101JI3B-100.0000T
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Microchip Technology DSC61XXB series XO (Standard), MEMS-based, 100 MHz, CMOS output, AEC-Q100, ±20 ppm, 4-VLGA, Tape & Reel.

Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

DSC6101JI3B-100.0000T specifications
ParameterValue
TypeXO (Standard)
SeriesDSC61XXB
MountingSurface Mount
Voltage1.71V ~ 3.63V
Current - supply3mA (Typ)
Frequency100 MHz
Frequency stability±20ppm
Operating temperature-40°C~85°C
Size (Dimension)0.098\" L x 0.079\" W (2.50mm x 2.00mm)
Height - seated0.035\" (0.89mm)
OutputCMOS
PackageTape & Reel (TR)
RatingsAEC-Q100
FunctionEnable/Disable
Base resonatorMEMS
Case4-VLGA

Product details

The DSC6101JI3B-100.0000T: The MEMS base eliminates quartz-specific failure modes — no startup reliability concerns, no shock-induced frequency jumps, and no crystal aging drift over the first year of field operation.

At 3 mA typical supply current, the oscillator's draw is negligible in a 1A automotive power budget — the same LDO feeding the MCU core can also supply this clock without derating. Pull the enable pin low to stop oscillation and drop the supply current to near-zero — useful for modules that must pass a low-quiescent-current sleep test per OEM specification.

The 4-pin land pattern is standard for MEMS oscillators in this footprint — no special via-in-pad or thermal relief required. The CMOS output drives a standard 15 pF load; route the clock trace with a 50-ohm characteristic impedance if the trace length exceeds 25 mm to avoid edge reflections at 100 MHz.

Frequently asked questions

Where can I buy DSC6101JI3B-100.0000T and how is it quoted?

Sourced through independent distribution channels.

What does the ±20 ppm frequency stability mean for my timing budget?

For a 500 Mbps CAN FD or 100BASE-T1 Ethernet PHY, this keeps the bit-time jitter well within the receiver's tolerance — no external PLL or VCXO needed.