The DSC6041JA3B-001.0240T: In a battery-backed always-on domain (CAN transceiver wake-up, RTC calibration, security monitor), the 1.3 mA draw is a small fraction of the sleep budget.
Frequency stability and timing margin
Frequency stability is specified at ±20 ppm total — this includes initial tolerance, temperature drift, and aging combined. For a 1.024 MHz clock, ±20 ppm translates to roughly ±20 Hz of absolute error. That is tight enough for CAN bus (which tolerates ±0.5% bit-rate error) and for general-purpose microcontroller clocking, but not tight enough for precision timekeeping or Ethernet PHY reference clocks.
The 4-pin land-grid array footprint is standard for MEMS oscillators in this form factor — no special via pattern or thermal pad required.
