48 MHz, 1.3 mA, and the power budget
The DSC6011JI2B-048.0000T: The 48 MHz output is a common clock for MCUs, FPGAs, and Ethernet PHYs. For a 48 MHz clock this means the maximum frequency error is ±1.2 kHz — tight enough for UART bit-rate tolerance and most SPI/I2C timing windows.
4-VLGA footprint and board integration
The compact footprint fits space-constrained layouts — think automotive sensor modules or portable instrumentation. Supplied in Tape & Reel (TR) — pick-and-place ready for volume assembly. No special handling beyond standard ESD precautions.