The DSC6011JI2B-048.0000: That disable current is low enough to leave the oscillator powered from a battery-backed rail in a telematics module or a body controller that wakes on a CAN message.
Frequency stability and timing margin
±25 ppm frequency stability covers the full temperature range and supply variation. For a 48 MHz clock, that is a ±1.2 kHz window — tight enough for a CAN bus bit-timing budget or a 100BASE-TX PHY reference where the total tolerance must stay under ±50 ppm including the downstream PLL.
4-VLGA package, 2.50 x 2.00 mm body, 0.89 mm seated height. The land pattern matches the standard 4-pad VLGA footprint — no hidden thermal pad underneath, so a standard hot-air rework profile for small QFN-style packages works. The MEMS die is inside the ceramic lid; no special bake-out required beyond the standard MSL handling for the package.