HCSL (High-Speed Current Steering Logic) is the common clock standard for PCIe, SATA, and Ethernet reference clocks; the 125 MHz outputs can serve a PCIe Gen 3/4 root complex while the 100 MHz pair drives the Ethernet PHY or FPGA fabric, all from one oscillator instead of two.
Package and layout: 20-VFQFN with exposed pad
Housed in a 5.00mm x 3.20mm, 20-lead VFQFN with an exposed pad, the part requires the pad to be soldered to a ground plane for thermal management — the MEMS oscillator draws minimal current, but the pad also provides a low-inductance ground return for the HCSL outputs. The 0.035" (0.90mm) height keeps it compatible with standard mezzanine card spacing. Supply voltage range of 2.25 V to 3.6 V covers 2.5 V and 3.3 V rails commonly used in networking and computing designs — no extra regulator needed if the board already has one of these rails.