Two reference clocks from one MEMS die
The DSC400-4334Q0023KI2 is a MEMS-based XO that delivers two independent output frequencies: 100 MHz on output 1 and 156.25 MHz on output 2. That pair — 100 MHz for the system bus or FPGA fabric clock, 156.25 MHz for the 10GbE or PCIe reference — lets a single oscillator serve two clock domains, saving a second crystal and its load caps. The output format is pin-selectable between HCSL and LVDS. HCSL is the native signaling for PCIe reference clocks; LVDS is common on FPGA clock inputs and SERDES. One part covers both without a level translator.
Industrial temp and ±25 ppm stability
Supply voltage spans 2.25 V to 3.6 V, so it runs from a 2.5 V or 3.3 V rail without a separate regulator.
Housed in a 20-VFQFN with exposed pad (5.00 mm x 3.20 mm, 0.90 mm height). The 0.50 mm pitch QFN demands a solder-paste stencil aperture that matches the pad geometry; a 4-mil stencil is typical.