Four timing lanes from one MEMS die
The DSC400-4111Q0112KI1T packs four independent clock outputs into a single 5.00 mm × 3.20 mm 20-VFQFN package: three lanes at 25 MHz (LVCMOS) and a fourth lane delivering either 100 MHz or 156.25 MHz in HCSL or LVCMOS. That replaces up to four discrete XOs with one device, cutting placement cost and board area on multi-rail timing trees for Ethernet switches, PCIe reference clocks, and FPGA multi-clock designs.
Supply tolerance and output compatibility
Runs from 2.25 V to 3.6 V — the same BOM rail serves 2.5 V and 3.3 V systems without a separate regulator. The mixed HCSL/LVCMOS output stage means the 156.25 MHz lane can drive a differential HCSL clock tree (common on PCIe Gen 1–3) while the three 25 MHz lanes stay single-ended for the system controller and PHY.
Industrial temperature and frequency hold
For an outdoor small-cell backhaul or a factory-floor PLC clock, this keeps the Ethernet link from dropping when the enclosure hits 70°C.
Microchip lists this as Active.