Quad-output MEMS XO with HCSL and LVCMOS lanes
Three lanes are fixed at 25 MHz each, supporting either HCSL or LVCMOS logic levels; the fourth lane is factory-programmed to 100 MHz or 156.25 MHz, making it a single-device clock source for a multi-rail FPGA or SoC clock tree. For a design that already uses the DSC400 family, this order code locks in a specific frequency plan — confirm the four output frequencies match your BOM before committing.
The 2.25V–3.6V supply range means this oscillator runs directly off a 2.5V or 3.3V rail without an intermediate LDO.
Active production, Tape & Reel packaging
The 0.90 mm height and 5.00 mm × 3.20 mm footprint fit within typical mezzanine card and module height budgets.