Quad-output LVDS clock with video and networking frequencies
The DSC400-3333Q0099KI2 is a MEMS-based XO that delivers four independent LVDS clock outputs from a single 20-VFQFN package — frequencies at 148.35 MHz and 148.5 MHz (Output 1), 156.25 MHz (Output 2), 208.333333 MHz (Output 3), and 197.8 MHz and 198 MHz (Output 4). The 148.35/148.5 MHz pair aligns with 3G-SDI and UHD-SDI video line rates; 156.25 MHz is the common reference for 10 GbE and SFP+ SerDes; 208.333333 MHz clocks 12G-SDI or PCIe Gen3; the 197.8/198 MHz output suits FPGA transceiver reference or 4G/5G baseband timing.
The exposed-pad package measures 5.00 mm × 3.20 mm with a height of 0.90 mm — the small footprint frees board area, but the central thermal pad requires a via-in-pad array to conduct heat to the ground plane and to anchor the part against reflow tombstoning.