Four LVDS clocks from one MEMS die
The DSC400-3333Q0099KI1 packs four independent LVDS output pairs into a single 5.00 x 3.20 mm 20-VFQFN package, replacing up to four discrete oscillators on the board. Output frequencies cover 148.35 MHz, 148.5 MHz, 156.25 MHz, 208.333333 MHz, 197.8 MHz, and 198 MHz — a spread that suits video clocking (148.5 MHz for 3G-SDI), Ethernet reference (156.25 MHz for 10GbE), and FPGA transceiver cores (208.333333 MHz).
MEMS reliability vs quartz startup
Supply and output gating
Supply range is 2.25 V to 3.6 V — the part runs on a 2.5 V or 3.3 V rail without a separate regulator. The enable/disable pin gates the LVDS outputs while keeping the PLL alive, so the downstream FPGA can halt its transceiver clocks without re-locking the oscillator.
Status is Active per Microchip's current lifecycle.