Four 80 MHz LVDS clocks from a MEMS resonator
Frequency stability is held to ±25 ppm across the full -40°C to 85°C industrial range, which keeps the clock edge jitter within the timing budget for 1 GbE or PCIe Gen1 interfaces without external PLL cleanup.
Supply flexibility and enable/disable control
The device operates from a 2.25 V to 3.6 V supply rail, covering 2.5 V and 3.3 V logic families without a separate regulator — one less BOM line to manage. An Enable/Disable function on each output lets the system power down unused clock lanes, reducing overall power draw and simplifying test-mode sequencing.
The 20-VFQFN exposed-pad package (5.00 mm x 3.20 mm, 0.90 mm height) requires a thermal pad on the PCB for heat sinking; the datasheet layout guide specifies the via pattern under the pad.