Dual-frequency LVDS clock source
The DSC400-3333Q0089KE2 is a MEMS-based XO delivering two LVDS outputs at 148.35 MHz and 148.5 MHz from a single 20-VFQFN package. These frequencies align with common video and broadcast clock domains, so a single oscillator can feed both the pixel clock and the data-rate clock without a second PLL. That holds the jitter budget for 1 GbE or 3G-SDI serial links without external compensation.
Supply flexibility and enable control
The supply range spans 2.25 V to 3.6 V, covering both 2.5 V and 3.3 V logic rails directly.
The 20-VFQFN with exposed pad (5.00 mm × 3.20 mm, 0.90 mm height) has a central thermal pad that must be soldered to a ground plane for proper heat dissipation. The pad is large enough that a hot-air rework station with a 6 mm nozzle can lift it cleanly if the board is preheated to 100°C — just don't rush the soak or you risk lifting the corner pads.