Dual-frequency LVDS clock for video timing
This MEMS-based XO outputs 148.35 MHz on one channel and 148.5 MHz on the other — the two frequencies that frame-rate generators in broadcast video gear switch between for 24p, 25p, and 30p formats. A single DSC400-3333Q0089KE1T replaces two separate cans and saves a slot on the board. The LVDS output pair keeps jitter low over the short differential traces to the FPGA or ASIC clock inputs.
Wide supply rail and ±50 ppm stability
Supply range from 2.25 V to 3.6 V covers both 2.5 V and 3.3 V logic rails without a separate LDO — one BOM line serves either rail.
20-VFQFN package — layout checklist
The 5.00 x 3.20 mm body with 0.90 mm height and an exposed thermal pad under the package requires a via-in-pad or a thermal via array on the PCB to pull heat to the ground plane.