Four 125 MHz LVDS clocks from a single MEMS resonator
The DSC400-3333Q0078KI2T delivers four independent 125 MHz LVDS outputs from a single MEMS resonator — a clean clock source for FPGAs, SoCs, or SerDes transceivers that need multiple synchronous reference clocks. The ±25 ppm frequency stability holds the timing budget across the full -40°C to +85°C industrial range, which matters for 1 GbE or PCIe Gen1/2 reference clocks where ppm error directly affects bit-error rate.
Supply flexibility and enable/disable control
The 2.25 V to 3.6 V supply range lets this XO run directly off a 2.5 V or 3.3 V rail without a separate LDO — one less component on the BOM. The enable/disable pin allows the outputs to be tri-stated for system-level power sequencing or test modes; the pin is active-high and referenced to the supply voltage.
Housed in a 20-VFQFN exposed pad package (5.00 mm × 3.20 mm, 0.90 mm height), the DSC400-3333Q0078KI2T requires a thermal pad on the PCB for both heat sinking and mechanical stability — the datasheet's recommended footprint is on page 7.