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Microchip Technology DSC400-3333Q0078KI1T — Crystals & Oscillators

DSC400-3333Q0078KI1T MEMS XO, LVDS, 125 MHz x4, Active

MPNDSC400-3333Q0078KI1T
Active

Microchip DSC400 series, XO (Standard), MEMS base resonator, 4 outputs at 125 MHz each, LVDS, ±50 ppm stability, 2.25V–3.6V supply, -40°C to 85°C, 20-VFQFN exposed pad, active production.

Microchip Technology DSC400-3333Q0078KI1T datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

DSC400-3333Q0078KI1T specifications
ParameterValue
TypeXO (Standard)
SeriesDSC400
Supply voltage2.25V ~ 3.6V
Frequency stability±50ppm
Frequency - output 1125MHz
Frequency - output 2125MHz
Frequency - output 3125MHz
Frequency - output 4125MHz
Operating temperature-40°C~85°C
Height0.035\" (0.90mm)
Size (Dimension)0.197\" L x 0.126\" W (5.00mm x 3.20mm)
OutputLVDS
PackageTape & Reel (TR)
FunctionEnable/Disable
Base resonatorMEMS
Case20-VFQFN Exposed Pad

Product details

Active MEMS oscillator with four 125 MHz LVDS lanes

Operating from 2.25 V to 3.6 V, it runs on a 3.3 V or 2.5 V rail without a separate LDO — the wide supply tolerance simplifies power-tree design when the oscillator shares a rail with the FPGA bank.

Industrial temperature grade and ±50 ppm stability

Frequency stability of ±50 ppm holds the output within 6.25 kHz of 125 MHz across the temperature range — tight enough for 1 GbE reference clocks and SERDES framing without external VCXO trimming.

Microchip lists the DSC400-3333Q0078KI1T as Active.

Frequently asked questions

Is DSC400-3333Q0078KI1T compatible with 3.3V systems?

Yes. The supply voltage range is 2.25 V to 3.6 V, so it runs directly from a 3.3 V rail without an additional regulator. The LVDS outputs swing 350 mV typical into a 100-ohm termination, compatible with standard LVDS receivers on FPGAs and ASICs at 3.3 V.

Does DSC400-3333Q0078KI1T have an enable/disable function?

Yes, the enable/disable function is built in. When disabled, the outputs enter a high-impedance state, which allows bus-sharing or power-down clock gating without a separate clock buffer.