Four 125 MHz LVDS clocks from a MEMS resonator
Each output runs at 125 MHz with ±50 ppm frequency stability, keeping the jitter budget tight for 10 GbE, PCIe Gen 3, or SATA link clocks without a separate PLL cleaning stage. Supply voltage spans 2.25 V to 3.6 V — a single 2.5 V or 3.3 V rail powers all four lanes, simplifying the power distribution on a mixed-voltage board.
Housed in a 20-VFQFN with exposed pad (5.00 mm x 3.20 mm, 0.90 mm height), the package demands a thermal via array under the pad for heat sinking — the MEMS die dissipates little heat, but the pad still needs a solid ground-plane connection for EMI containment.