Four 125 MHz LVDS lanes from one MEMS resonator
Each output runs at the same frequency — useful for clocking multiple FPGA banks, SerDes lanes, or Ethernet PHYs from one reference without splitting a single-ended signal. Supply voltage spans 2.25V to 3.6V, so it sits on a 2.5V or 3.3V rail without an extra LDO.
20-VFQFN footprint and board layout notes
The 20-VFQFN Exposed Pad package measures 5.00 mm x 3.20 mm with a 0.90 mm height.
