Four 125 MHz LVDS clocks from one MEMS die
The DSC400-3333Q0078KE1 generates four identical 125 MHz LVDS outputs from a single MEMS resonator — a clean fit for clocking four FPGA transceiver lanes or a multi-channel SERDES reference without external fanout buffers.
Supply rail flexibility and package footprint
The 2.25V to 3.6V supply range lets the oscillator run off a 2.5V or 3.3V rail directly — no separate LDO needed, which simplifies the power tree for dense clock distribution. Housed in a 20-VFQFN with exposed pad (5.00 mm x 3.20 mm body), the part requires a thermal via array under the pad for proper ground-plane heat sinking; the 0.90 mm height clears typical board-to-board spacing.
The part is eligible for new designs and carries no last-time-buy deadline.