Quad-output MEMS oscillator with LVDS signalling
Output bank 1 provides 25MHz, 50MHz, 125MHz, and 150MHz; output bank 2 provides 100MHz and 156.25MHz – a fixed frequency set that suits multi-rate Ethernet, FPGA reference clocks, or base station timing where multiple synchronous rails are needed. The MEMS resonator eliminates quartz start-up variability and shock sensitivity, making this oscillator a drop-in replacement for standard crystal oscillators in designs that already accept LVDS levels.
The 2.25V to 3.6V supply range means the same part runs on a 2.5V or 3.3V rail without a separate level translator – the LVDS output common-mode voltage tracks the supply, so the receiving FPGA or SerDes input sees a valid differential swing across the full range.
Enable/disable function and package footprint
The 20-VFQFN with exposed pad (5.00mm x 3.20mm, 0.90mm height) requires a thermal pad on the PCB for heat sinking; the 0.50mm pitch pads demand careful fan-out but keep the footprint smaller than a comparable 14-pin SOIC oscillator bank.
