Why a MEMS XO beats four quartz cans
Quad-output architecture: one part, four clocks
The device outputs LVCMOS on the 12 MHz port and LVDS on the three 50 MHz ports, covering a typical SoC + Ethernet PHY + FPGA clock tree from one oscillator. Supply voltage spans 2.25V to 3.6V, so it works on 2.5V or 3.3V rails without a separate regulator.
Housed in a 20-VFQFN with exposed pad, the 5.00mm × 3.20mm footprint and 0.90mm height fit dense PCB layouts where vertical clearance is tight — think blade servers or compact switch designs.