Four-output LVPECL clock source for timing trees
With ±50 ppm frequency stability and a 2.25V to 3.6V supply range, it can serve as a common clock source for multiple high-speed serial links or FPGA banks without needing separate oscillators per lane.
Housed in a 20-VFQFN exposed-pad package (5.00 mm x 3.20 mm, 0.90 mm height), the thermal pad must be soldered to a ground plane for proper heat dissipation — the datasheet layout recommendation should be followed for reliable LVPECL signal integrity at 125 MHz.