Four-output MEMS oscillator for clock-tree consolidation
It replaces up to four discrete oscillators, saving board area and reducing BOM line count. Output frequencies are 100 MHz, 156.25 MHz, 125 MHz, and 25 MHz — a combination that directly serves 1GbE/10GbE MAC/PHY reference clocks, FPGA transceiver banks, and processor core or peripheral clocks without external PLLs or dividers. Each output can be independently configured as LVCMOS or LVDS, giving the layout engineer flexibility to drive single-ended or differential clock trees from the same device.
Industrial temperature grade and supply-range flexibility
Supply voltage spans 2.25 V to 3.6 V, covering 2.5 V and 3.3 V rails common in mixed-signal designs. The wide input range also provides headroom for noisy rails without an external LDO.
Package, footprint, and enable/disable control
Housed in a 20-VFQFN with exposed pad (5.00 mm x 3.20 mm, 0.90 mm height), the package requires a thermal pad on the PCB for heat sinking and mechanical stability.
For volume requirements, confirm reel or tray options at RFQ.