Three 100 MHz HCSL lanes from a MEMS resonator
HCSL is the differential signalling standard used for PCIe reference clocks — the 100 MHz frequency matches the PCIe Gen 1/2/3 base clock rate, so this part can serve as the common clock source for multiple PCIe lanes or SerDes channels on a board. The supply voltage range of 2.25 V to 3.6 V lets it run off either a 2.5 V or 3.3 V rail without an intermediate regulator.
Temperature grade and package constraints
It fits indoor telecom switches, server motherboards, and office networking gear — not outdoor base stations or under-hood automotive. The 20-VFQFN exposed-pad package (5.00 mm x 3.20 mm, 0.90 mm height) requires a thermal pad on the PCB for heat sinking; the pad also provides a low-inductance ground return for the HCSL outputs.
