Three fixed clocks from one MEMS resonator
Each output can be configured as HCSL or LVCMOS, giving you the flexibility to drive a PCIe reference clock on one lane and a logic-level clock on another from the same package.
For a 100 MHz carrier, that translates to a maximum drift of ±5 kHz — tight enough for most Ethernet, USB, and general-purpose processor clocks without external trimming. The 2.25 V to 3.6 V supply range covers 2.5 V and 3.3 V rails directly. No extra LDO needed if your board already runs one of those voltages.
Housed in a 20-VFQFN with exposed pad (5.00 mm x 3.20 mm footprint, 0.90 mm height).
