Dual 100 MHz HCSL clock for PCIe and SerDes reference
The DSC400-0404Q0058KI1T is a MEMS-based XO delivering two 100 MHz HCSL outputs from a single 20-VFQFN package — a common reference clock for PCIe Gen1/2/3, 10GbE, and FPGA transceiver banks that need a low-jitter differential pair without an external PLL.
Supply-rail flexibility and decoupling layout
The 2.25 V to 3.6 V supply range lets this oscillator sit on a 2.5 V or 3.3 V rail without an extra LDO — useful when the FPGA bank voltage is already set.
Active lifecycle with no obsolescence risk
The MEMS resonator gives better long-term aging and shock tolerance than quartz, which matters for high-reliability deployments. Sourced per RFQ; availability confirmed at quote time.
Frequency stability and output type for signal integrity
±50 ppm frequency stability over the full industrial temperature range keeps the clock edge within the receiver's timing budget for 100 MHz HCSL — the differential swing and common-mode voltage match the PCIe and SATA reference-clock specs without external termination resistors.