MEMS resonator with HCSL drive for 100 MHz clock trees
HCSL (High-Speed Current Steering Logic) is the common reference format for PCIe, SATA, and Ethernet PHY clocking — the differential swing and common-mode voltage match the input requirements of those SerDes PLLs without external level shifting. For a 100 MHz reference, ±25 ppm translates to a ±2.5 kHz absolute frequency error at the PLL input — well within the capture range of a standard PCIe Gen 3 clock recovery loop.
Supply voltage flexibility and enable/disable function
The supply range spans 2.25 V to 3.6 V, covering both 2.5 V and 3.3 V rails without an intermediate regulator.
Package footprint and board-level considerations
Housed in a 20-VFQFN with exposed pad, 5.00 mm × 3.20 mm body, 0.90 mm height. The 0.50 mm pitch QFN pads require a solder-mask-defined pad on the PCB; NSMD (non-solder-mask-defined) pads risk solder bridging during reflow.
Lifecycle status and supply posture
Product status is Active per Microchip's current lifecycle designation. The DSC400 series is an established MEMS oscillator family with multiple output configurations — the 0404Q0058KE2T variant is a standard catalogue order code, not a custom trim.