HCSL output for PCIe and SerDes reference clocks
The DSC400-0404Q0058KE2 delivers a 100 MHz HCSL output — the standard logic family for PCIe reference clocks, requiring no external level translation when feeding a PCIe Gen1/2/3 PHY or a SerDes PLL.
Start-up time is typically under 5 ms, compared to 10–20 ms for a quartz-based XO — the system clock is valid before the FPGA finishes configuration.
Rated for 2.25 V to 3.6 V supply — the same BOM line works on a 2.5 V or 3.3 V rail without changing the oscillator order code. The -20 to 70 °C commercial range covers indoor telecom, office networking, and test equipment; for outdoor or engine-bay deployment, the DSC400 family includes wider-temperature variants.
Active lifecycle and package footprint
The 20-VFQFN exposed pad (5.00 mm × 3.20 mm, 0.90 mm height) requires a thermal via array under the pad for the exposed die attach — the datasheet layout recommendation keeps the junction temperature within the commercial range.
