MEMS oscillator for PCIe clocking
It delivers two 100 MHz HCSL outputs from a single device, which directly feeds the reference clock inputs of a PCIe switch or FPGA transceiver bank. HCSL (High-Speed Current Steering Logic) is the standard output type for PCIe Gen1 through Gen4 reference clocks — no external level translation needed if the destination is a PCIe PHY or Intel PCH.
Supply and temperature fit
Operating supply spans 2.25V to 3.6V, covering both 2.5V and 3.3V rails without a dedicated LDO. Frequency stability is ±50 ppm, which keeps the PCIe reference within the ±300 ppm total tolerance budget for Gen3 even after aging and temperature drift.
Housed in a 20-VFQFN with exposed pad (5.00mm x 3.20mm body, 0.90mm height).