Dual HCSL outputs for PCIe clock trees
The DSC400-0404Q0007KE1 delivers two HCSL outputs at 100 MHz and 156.25 MHz, the standard reference frequencies for PCIe Gen 1/2/3 and 10 GbE SerDes. The HCSL logic level swings 700-900 mV peak-to-peak into a 50-Ω termination to ground, matching the differential input requirements of most PCIe clock buffers and PHYs without external level translation.
20-VFQFN footprint and thermal pad
The 20-VFQFN package measures 5.00 mm x 3.20 mm with a 0.90 mm height. The 0.50 mm pitch QFN pads require a solder-mask-defined pad with a 0.25 mm stencil aperture for reliable solder joint formation. Supply voltage range is 2.25 V to 3.6 V, covering 2.5 V and 3.3 V rails common in networking and computing platforms. The ±50 ppm frequency stability over -20°C to +70°C keeps the PCIe spread-spectrum clocking within the ±0 ppm to -5000 ppm downspread window without external compensation.