MEMS clock with three independent LVDS outputs
The DSC400-0333Q0032KE1 is a MEMS-based XO (Standard) that outputs three separate LVDS clock frequencies from a single 20-VFQFN package: 24.576 MHz, 24 MHz, and 25 MHz. LVDS signalling keeps the edge rates clean and common-mode noise rejection high, which matters when the clock fan-out crosses a backplane or drives an FPGA bank that is sensitive to deterministic jitter.
Supply flexibility and enable/disable control
Runs from a 2.25V to 3.6V supply rail, so it can drop directly onto a 2.5V or 3.3V plane without an extra regulator.
Housed in a 20-VFQFN with exposed pad — the 5.00 mm x 3.20 mm footprint and 0.90 mm height fit dense PCIe or SFP+ line-card layouts where height clearance is tight.
Availability confirmed at RFQ.