Dual 80 MHz LVDS clock source for timing trees
Frequency stability is ±25 ppm across the -20°C to +70°C commercial temperature range, keeping the timing budget tight for 10/100/1000 Ethernet or base-station reference clocks.
The 2.25 V to 3.6 V supply range covers both 2.5 V and 3.3 V rails — no extra regulator needed when the board runs mixed supplies. LVDS output levels track the supply, so 3.3 V operation delivers full 350 mV swing into 100 Ω termination.
Package and PCB layout notes
The 20-VFQFN with exposed pad (5.00 mm x 3.20 mm body, 0.90 mm height) requires a thermal via array under the paddle for heat sinking and ground return. The 0.50 mm pitch perimeter pads fan out on a 4-layer board without microvias.