MEMS oscillator with dual LVDS outputs
The LVDS output pair provides low-jitter differential signaling suitable for high-speed data converters, FPGAs, or SerDes reference clocks where common-mode noise rejection matters. The supply voltage spans 2.25V to 3.6V, covering common 2.5V and 3.3V rails.
Housed in a 20-VFQFN exposed-pad package measuring 5.00mm x 3.20mm with a seated height of 0.90mm.
The DSC400 series remains a current design-in candidate for new builds.
