MEMS clock source with dual 80 MHz LVDS lanes
LVDS signalling keeps the edge rates clean across short PCB traces — useful when both clocks feed separate FPGAs or SerDes transceivers on the same board.
Supply range and package footprint
The supply voltage spans 2.25V to 3.6V, covering 2.5V and 3.3V rails without an external regulator. The 20-VFQFN exposed-pad package (5.00 mm x 3.20 mm, 0.90 mm height) requires a thermal via pattern under the pad for heat sinking — the datasheet layout recommendation should be followed to keep the junction temperature within limits.
