Dual-frequency 148.5 / 148.35 MHz LVDS XO for broadcast video
The DSC400-0303Q0086KE2 is a MEMS-based XO that outputs two LVDS clock frequencies: 148.5 MHz on output 1 and 148.35 MHz on output 2. Those are the standard pixel clocks for 1080p and 1080i/720p video, respectively — this part is built for broadcast infrastructure, video routers, and SDI interface cards where the two rates must coexist on the same board.
±25 ppm stability and supply range for a clean clock tree
Total frequency stability of ±25 ppm covers temperature, supply variation, and the MEMS resonator's own drift — tight enough to keep the serial digital interface within SMPTE jitter budgets without an external VCXO or PLL cleanup stage. The supply voltage range of 2.25 V to 3.6 V means this oscillator can run directly from a 2.5 V or 3.3 V rail without an intermediate LDO. The LVDS output swings are referenced to the supply, so a 3.3 V rail gives the full 350 mV typical swing into a 100-Ω termination.
20-VFQFN footprint and layout notes
Housed in a 20-VFQFN with exposed pad, 5.00 mm × 3.20 mm body, 0.90 mm height.