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Microchip Technology DSC400-0244Q0009KI1 — Crystals & Oscillators

DSC400-0244Q0009KI1 MEMS XO – Dual 100 MHz HCSL/LVPECL

MPNDSC400-0244Q0009KI1
Active

Microchip Technology DSC400 series MEMS XO (Standard), dual 100 MHz outputs, HCSL/LVPECL, 2.25-3.6 V supply, ±50 ppm stability, -40 to +85°C, 20-VFQFN exposed pad.

Microchip Technology DSC400-0244Q0009KI1 datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

DSC400-0244Q0009KI1 specifications
ParameterValue
TypeXO (Standard)
SeriesDSC400
Supply voltage2.25V ~ 3.6V
Frequency stability±50ppm
Frequency - output 1100MHz
Frequency - output 2100MHz
Operating temperature-40°C~85°C
Height0.035\" (0.90mm)
Size (Dimension)0.197\" L x 0.126\" W (5.00mm x 3.20mm)
OutputHCSL, LVPECL
PackageTube
FunctionEnable/Disable
Base resonatorMEMS
Case20-VFQFN Exposed Pad

Product details

Dual 100 MHz MEMS oscillator with HCSL/LVPECL drive

This dual-output architecture serves as a single-device clock source for PCIe reference clocks or high-speed SerDes lanes, replacing two discrete oscillators and saving board space.

Operating from 2.25 V to 3.6 V, the oscillator spans 2.5 V and 3.3 V rails common in FPGA and ASIC power trees.

Housed in a 20-VFQFN with exposed pad (5.00 mm x 3.20 mm, 0.90 mm height), the package requires a thermal pad on the PCB for heat dissipation.

Frequency stability and enable/disable function

With ±50 ppm frequency stability, the part holds tight timing margins for 100 MHz clock trees without external compensation.

Frequently asked questions

What is the frequency and output type of DSC400-0244Q0009KI1?

The DSC400-0244Q0009KI1 provides two 100 MHz outputs, each configurable as HCSL or LVPECL logic levels. This means a single oscillator can drive a PCIe reference clock (HCSL) and a SerDes PLL (LVPECL) simultaneously.

Does DSC400-0244Q0009KI1 support enable/disable?

Yes, the part includes an enable/disable function that tri-states the outputs. This is useful for power sequencing or test modes where the clock must be gated without removing supply voltage.