Dual 100 MHz differential outputs for clock-tree fan-out
That means a single oscillator can clock a PCIe reference and a SerDes PLL from the same package, saving a second oscillator slot on the BOM.
Unlike a quartz crystal, MEMS has no activity dips or startup reliability issues across temperature—the frequency stays within that window from first power-up. For a 100 MHz clock, ±25 ppm is 2.5 kHz of absolute error, well within the capture range of most PLLs.
Wide supply range and enable/disconnect for power sequencing
The supply input accepts 2.25 V to 3.6 V, so the same part works on a 2.5 V FPGA bank or a 3.3 V ASIC rail without an extra LDO.
20-VFQFN package: layout and thermal pad considerations
Housed in a 20-lead VFQFN with an exposed pad, the DSC400 measures 5.00 mm × 3.20 mm with a 0.90 mm height. The 0.50 mm pitch QFN demands careful fan-out; a two-layer board can route it if the inner pads connect to vias under the package.
Active lifecycle and sourcing through independent distribution
Sourced through independent distribution, quantities are confirmed per RFQ; no minimum order threshold is imposed.