Dual LVPECL outputs at 167.1875 / 173.28125 MHz
The DSC400-0202Q0108KE1 delivers two LVPECL clock outputs: one at 167.1875 MHz and one at 173.28125 MHz, from a single MEMS resonator. These frequencies are common reference clocks for 10G Ethernet PHYs and high-speed SerDes transceivers — the 167.1875 MHz output often feeds the MAC side while the 173.28125 MHz drives the line-side PLL.
Supply flexibility and enable control
The supply voltage range spans 2.25 V to 3.6 V, covering both 2.5 V and 3.3 V rails. This means you can power it from an existing 3.3 V FPGA bank or a 2.5 V SerDes rail without a dedicated LDO — the oscillator's internal regulation handles the variation. When disabled, the outputs enter a high-impedance state, which is useful for sharing a clock bus or for boundary-scan testing.