Dual LVPECL clock source for 1G/10G Ethernet and CPRI
The DSC400-0202Q0106KI2T is a MEMS-based XO that delivers two independent LVPECL clock outputs at 153.6 MHz and 155.46875 MHz — frequencies commonly used as the reference for 1G/10G Ethernet PHYs and CPRI SerDes lanes.
Supply flexibility and output termination
The wide 2.25 V to 3.6 V supply rail means the oscillator runs directly from a 2.5 V or 3.3 V rail without an intermediate LDO. LVPECL outputs require DC termination — typically 50 Ω to Vcc - 2 V — so the board must include the resistor network or AC-coupling caps before the receiver.
Microchip lists the DSC400-0202Q0106KI2T as Active.
20-VFQFN exposed-pad layout notes
The 5.00 mm x 3.20 mm, 20-lead VFQFN package has an exposed pad on the bottom.
