Two clocks, one package — what the dual output buys you
The DSC2311KI2-R0045 delivers two independent CMOS clock frequencies from a single MEMS resonator: 50 MHz on output 1 and 24 MHz on output 2. That means a processor core and its peripheral bus — or an FPGA fabric and its Ethernet MAC — can share one oscillator footprint instead of two, saving board space and reducing the BOM line count.
The 2.25 V to 3.6 V supply range covers 2.5 V and 3.3 V logic rails without a separate LDO. A design running a 3.3 V FPGA core and a 2.5 V I/O bank can drop this oscillator on either rail and keep the same timing budget.
The 6-VDFN package measures 2.50 mm x 2.00 mm with a 0.90 mm seated height — small enough for a space-constrained sensor module or a multi-layer backplane card. The 0.50 mm pitch pads require a fine-pitch solder stencil; a 4-mil stencil thickness with a 1:1 aperture-to-pad ratio is typical for this land pattern.