Dual-frequency HCSL clock for PCIe and SerDes reference
This dual-frequency capability is common in networking and storage designs where a single oscillator feeds both a PCIe reference clock (100 MHz) and a SerDes or Ethernet PHY reference (125 MHz), saving a second oscillator slot on the BOM. Supply voltage spans 2.25 V to 3.6 V, covering 2.5 V and 3.3 V rails without a separate LDO. The wide range also absorbs ripple on a shared 3.3 V rail as long as the minimum is respected. For a 100 MHz output, that is ±2.5 kHz absolute — tight enough for 1000BASE-T and PCIe Gen1/2 reference jitter budgets.
Packaged in a 14-VFQFN with exposed pad (3.20 mm x 2.50 mm, 0.90 mm height).
HCSL (High-Speed Current Steering Logic) is the standard output format for PCIe reference clocks. The differential pair delivers a 700 mV swing into a 50-Ω termination to ground at the receiver. The MEMS resonator eliminates the crystal load-capacitance tuning step — the oscillator is factory-trimmed and ready to drive the clock tree.