154 MHz LVDS clock with MEMS reliability
Supply voltage and output compatibility
Runs from a 2.25 V to 3.6 V supply, so it sits on a 2.5 V or 3.3 V rail without an extra regulator. The LVDS output is a differential pair — 154 MHz is a common reference for SerDes, Ethernet PHYs, or FPGAs that need a low-jitter clock source.
The 14-SMD no-lead package measures 3.20 mm x 2.50 mm with a 0.90 mm height, a compact footprint that fits tight board layouts.
Listed as Active by Microchip.
