Dual 125 MHz HCSL outputs from a MEMS resonator
The DSC2044FL1-H0005 delivers two identical 125 MHz HCSL clock outputs from a MEMS-based resonator, eliminating the quartz crystal start-up and aging concerns in a standard XO. HCSL (High-Speed Current Steering Logic) is the native signaling for PCIe Gen1/2/3 reference clocks and Ethernet PHY interfaces, so this part drops straight into a typical 100 MHz or 125 MHz fan-out tree without a level translator.
The wide supply range of 2.25 V to 3.6 V lets it share a rail with a 2.5 V or 3.3 V FPGA bank without a separate LDO.
14-VFQFN package and enable/disable function
Housed in a 14-VFQFN exposed-pad package measuring 3.20 mm x 2.50 mm with a 0.90 mm height, the part fits tight PCIe add-in-card or mezzanine layouts.