Dual 100 MHz HCSL clock source – MEMS reliability
HCSL (High-Speed Current Steering Logic) is the typical reference clock for PCIe Gen1/2/3, Ethernet PHYs, and FPGA transceivers – the 60 mA max supply current covers both output lanes, making it a single-chip replacement for a pair of discrete oscillators.
Temperature grade and supply flexibility
The supply voltage spans 2.25 V to 3.6 V, so it runs from a 2.5 V or 3.3 V rail without an extra regulator.
Housed in a 14-VFQFN with exposed pad (3.20 mm x 2.50 mm, 0.90 mm height), the package requires a thermal pad on the PCB for heat sinking – the exposed paddle must be soldered to a ground plane to keep junction temperature within limits. The 0.50 mm pitch QFN demands careful fan-out; a 4-layer board with microvias under the pad is typical for production.
RoHS compliance is standard for this series (no explicit exemption noted).