Dual 100 MHz HCSL clock from a MEMS resonator
HCSL (High-Speed Current Steering Logic) is the standard output format for PCIe Gen1 through Gen4 reference clocks. The 100 MHz frequency matches the base PCIe reference exactly, so the oscillator feeds the PLL without an intermediate frequency multiplier.
For a 100 MHz clock, that is a maximum deviation of 5,000 Hz, well within the ±300 ppm tolerance that most PCIe reference clock receivers require.
2.25V–3.6V supply with enable/disable function
The supply voltage range of 2.25V to 3.6V lets the oscillator share a 2.5V or 3.3V rail without an intermediate LDO.
14-VFQFN exposed pad layout considerations
The 14-VFQFN exposed pad package (3.20 mm × 2.50 mm body, 0.90 mm height) requires a thermal via array under the pad to conduct heat to the ground plane and to provide a low-inductance return path for the HCSL outputs.