MEMS clock source with HCSL drive
HCSL (High-Speed Current Steering Logic) is the common reference format for PCIe, SATA, and Ethernet PHY clock trees — the differential pair drives 50 Ω to ground at the receiver, so the termination resistors are already on the load side.
Supply range and disable current
Supply voltage spans 2.25V to 3.6V, covering common 2.5V and 3.3V rails without an extra LDO. Maximum draw is 60 mA typical when enabled; the disable function drops it to 23 mA max — useful for power gating in a multi-clock domain design where the oscillator feeds a peripheral that sleeps.
Housed in a 14-VFQFN exposed pad package measuring 3.20 mm x 2.50 mm with a 0.90 mm profile.