Dual-output HCSL clock generator for PCIe and Ethernet
The DSC2044FE1-H0003T is a MEMS-based XO that generates two HCSL outputs simultaneously: 100 MHz on Output 1 and 125 MHz on Output 2, with an additional 156.25 MHz option on Output 2. HCSL (High-Speed Current Steering Logic) is the standard differential signalling for PCIe reference clocks — this part directly drives a PCIe Gen 1/2/3 PHY without an external level translator. The ±50 ppm frequency stability over -20°C to +70°C meets the ±50 ppm requirement for PCIe Gen 1/2/3 reference clocks, eliminating the need for external temperature compensation.
Supply voltage and power management
The 2.25V to 3.6V supply range covers both 2.5V and 3.3V rails — a single BOM line works across different voltage domains without a dedicated regulator. Maximum supply current is 60 mA typical; the enable/disable pin drops consumption to 23 mA in the disabled state, allowing power gating in sleep modes without an external load switch.
The 0.50 mm pitch QFN footprint demands tight solder-paste stencil aperture control; a 0.125 mm stencil thickness with 1:1 aperture-to-pad ratio is typical for this class of package.