MEMS-based dual-output clock with LVDS signalling
Output 1 supports 10, 30, 50, 80, 100, and 160 MHz; Output 2 adds 60, 120, 180, and 200 MHz — covering common FPGA reference, Ethernet, and serial-link rates without a second oscillator.
The 2.25V to 3.6V supply range spans 2.5V and 3.3V logic rails, so the same part can feed a 3.3V FPGA bank and a 2.5V transceiver without a dedicated regulator.
Housed in a 14-VFQFN Exposed Pad package measuring 3.20 mm x 2.50 mm with a 0.90 mm height, the DSC2033FI2-F0032 fits dense PCB layouts where height is constrained.