Dual LVDS clock sourcing for 150 MHz lanes
The DSC2033FI2-F0003T delivers two identical 150 MHz LVDS outputs from a single MEMS resonator, eliminating a second oscillator when a design needs a differential clock pair for a dual-lane SERDES or two independent PLLs. LVDS signaling keeps the 150 MHz edges clean across a few inches of FR4 trace—no single-ended noise coupling into adjacent analog supplies.
