Output 1 can be set to 100 MHz, 106.25 MHz, 125 MHz, or 156.25 MHz; Output 2 offers 25 MHz, 50 MHz, 100 MHz, 125 MHz, or 156.25 MHz — covering common Ethernet, PCIe, and FPGA reference frequencies without a second oscillator.
±25 ppm stability across full temperature range
The supply range spans 2.25 V to 3.6 V, so the same oscillator can feed a 2.5 V FPGA bank and a 3.3 V Ethernet PHY without a dedicated regulator — the Enable/Disable function lets the system gate the output when the downstream device is idle. Typical supply current is 32 mA with both outputs active; disabling the outputs drops consumption to 23 mA max — useful for power-sensitive applications where the clock can be stopped during sleep.