MEMS oscillator at 19.2 MHz – fit and output
Output is LVCMOS, the most common logic level for clocking MCUs, FPGAs, and SoCs.
Supply range and stability over temperature
For a 19.2 MHz clock, ±25 ppm translates to ±480 Hz maximum deviation — tight enough for UART baud-rate generation and most MCU clock trees without a separate PLL.
Housed in a 4-VFLGA package measuring 2.00mm x 1.60mm with a seated height of 0.89mm. That is a small land-grid array — the four pads are underneath, so the PCB footprint needs a solder-paste stencil with apertures matched to the pad geometry. No exposed leads to route; the fan-out is via micro-vias or short traces to the nearest via-in-pad.
Listed as Active with a current lifecycle stage — no end-of-life notice, no NRND flag.